, Singapore
Dr. Byung Joon Han, co-founder and CEO of Silicon Box [Photo from Silicon Box]

Silicon Box breaks bottleneck in chiplet packaging with sub-5-micron technology

The company’s technology reduces chiplet-based system packaging costs by up to 90%.

In creating chips, designers have the propensity to prioritise manufacturing ease over performance. To eliminate any compromise, Silicon Box has come up with a chiplet integration technology that can expedite chiplet design cycles and reduce the cost of new devices.

Through its sub-5-micron technology proprietary fabrication method, Silicon Box has the “ability to package chiplets with the shortest interconnections,” leading the way for semiconductor integration whilst offering cost benefits to its partners.

Speaking to the Singapore Business Review, Dr. BJ Han, CEO and co-founder of Silicon Box, underscored that whilst the concept of chiplets is already well accepted across the industry, there is a bottleneck in advanced packaging capability and capacity.

“Our technology uses the shortest interconnections and the world’s first standardised large-format production for chiplet integration,” Dr. Han said. “Our approach has led to the highest electrical performance in terms of speed and bandwidth, the best thermal performance, and the highest reliability by eliminating material interfaces.”

 By its own computation, Silicon Box has attained the improvement of electrical performance by over 50% and, at the same time, lowered power consumption by over 40%. This breakthrough is crucial because, as Dr. Han explained: “reducing thermal output means less power is required to cool the device, reducing energy use.”

To address the “missing link” in the “transformational movement towards chiplet adoption, Dr. Han co-founded Silicon Box with Dr. Sehat Sutardja and Weili Dai who were CEO and President at Marvell Technology Group, respectively.
“We are ‘box’-ing semiconductors in better ways!” said Dr. Han.

Apart from shortening the design cycle of chiplets and lowering new device costs, Silicon Box’s technology also allows faster-time-to-market for its partners involved in areas such as artificial intelligence (AI), data centres, electric vehicles (EVs), mobile, and wearables, according to Michael Han, head of business at Silicon Box.

Michael Han, head of business at Silicon Box [Photo from Silicon Box]

“Our technology and manufacturing process lowers packaging costs for chiplet-based systems by up to 90%, whilst producing chips at high volume. This is because we are able to minimise the form factor of system packages, and manufacture in a large format,” he said.
In July 2023, Silicon Box opened a 750,000 square feet semiconductor factory in Tampines.

The Silicon Box factory in Tampines. [Photo from Silicon Box]

 “The factory houses a state-of-the-art production line equipped to execute a one-of-a-kind, large-format fabrication method that improves the design cycle of chiplets,” he said.
The Silicon Box business head said they are already working towards bringing the factory to full capacity and “exploring opportunities to replicate it in other locations” where there’s high demand for their services.

[Photo from Silicon Box]

“Our technology can support a broad range of applications, and we have observed widespread interest and demand in our solutions, across different industries and the regions where they are based,” Michael said.
“We believe Silicon Box has catalysed greater creativity and enthusiasm in chiplet adoption to propel the semiconductor industry forward and to support the strategic silicon aspirations for diverse geopolitical blocs and industries,” he added.
Apart from expansion, Dr. Han told the Singapore Business Review that Silicon Box is also working on “the most advanced chiplet integration” particularly for AI, high-performance computing (HPC), mobile computing, data centres, electric vehicles, mobile devices, and wearables.
Silicon Box will utilise its current funding of US$410m for their plans and projects.

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